搜索资源列表
VerilogHDLTestBenchPrimer
- 讲解Verilog 的testbench的书写方法。-on Verilog testbench writing.
WritingTestbenches
- 编写testbench的超好教程，网上这种资料比较少。(Kluwer) Writing Testbenches--Functional Verification of HDL Models.pdf
how to write testbench
- 很好的，适合初学者Writing Efficient Testbenches
VHDL--testbench
- VHDL 的testbench 编写风格及技巧，有助利用modelsim做仿真，一看就会！-The testbench VHDL writing style and skills will help make using modelsim simulation, a look will be!
jibengongtestbench
- testbench的基本写法，双口ram,双端口的编写 -The basic writing testbench, dual-port ram, dual-port the preparation of
Lecture_Verification
- Writing testbench in verilog
writing-efficient-testbench
- 如何编写FPGA测试代码，XILINX官方资料-How to write test code for FPGA, XILINX official information
TestBench_Primer
- 是学习数字电路设计verilog语言，及Writing testbench的首先好书。-Writing testbench
testbench(vhdl)
- 是学习数字电路设计verilog语言，及Writing testbench的首先好书。-wrting testbench
writing-testbench
- 教你如何写VHDL或VerilogHDL的testbench文件，非常有利于FPGA的波形仿真-Teaches you how to write VHDL or VerilogHDL the testbench file, is very conducive to the waveform simulation of FPGA
Writing-Testbenches--
- 介绍如何使用system verilog搭建testbench。-introduce how to use the system verilog to writing testbench
Writing-Testbenches-using-System-Verilog
- writing testbench in system verilog
verilog-testbench--technique
- verilog testbench的写法和技巧，适合初学者-Verilog testbench of writing and techniques for beginners
verilog-testbench-preliminary
- 硬件描述语言verilog的testbench的写作方法-the writing method of the testbench of verilog
VHDL-TESTBENCH
- 这是一篇用VHDL编写testbeach测试文件的详细讲解资料，举例讲解详细易懂，很实用-This is a VHDL explain in detail the information writing testbeach test file, for example, to explain in detail to understand, it is practical
Janick-Bergeron-Writing-Testbenches-Functional-Ve
- WRITING TESTBENCHES Functional Verification of HDL Models Good Book for testbench
Testbench--Study
- testbench顾名思义就是一个测试台，它对外没有接口，所以实体部分为空，但它要对要测试的器件提供激励信号，这其实就是最简单的testbench，本文介绍了Testbench的书写-testbench name suggests is a test bed, it is no interface to the external, physical part of it is empty, but it should provide a stimulus to the device under
Modelsim_Steps_-to_-run_-testbench
- Writing test bench in using VHDL.
Writing_Testbench
- Writing_Testbench 一本介绍testbench非常好的一本英文书籍。-Writing Testbench a very good testbench describes an English book.
verilog add4
- 分两部分，基于verilog的四位和八位加法器设计，用synopsys的VCS仿真工具进行功能仿真，掌握基本的makefile编写以及linux操作。(Divided into two parts, four and eight adder based on verilog design, function simulation with synopsys VCS simulation tools, master the basic makefile writing and Linux.)